A digital-to-analog conversion circuit, also referred to as a DAC, is a decoding device that receives a digitally coded signal and provides corresponding analog output current or voltage signal. Accordingly, a DAC is often used to as an interface between a digital and an analog system.
FIG. 1 is a simplified high-level block diagram of a conventional DAC 10. The input to DAC 10 is a digital word D that includes a stream of binary bits. The output analog signal, which may be a current or a voltage, is related to the input as follows:A=KVrefDwhere K is a scaling factor, and Vref is a reference voltage. D may be represented as:D=b1/21+b2/22+ . . . +bN/2N where N is the total number of bits, and b1, b2 . . . are the bit coefficients, quantized to be either a 1 or a 0.
A voltage-scaling DAC, also referred to herein below as VDAC, generates an analog output voltage signal by selectively tapping a voltage-divider resistor string connected between the reference voltage and the ground. A number of switches, e.g., CMOS switches, and/or decoding logic is used to select and pass one of the tapped voltages as the analog output voltage signal. Two conventional decoding methods exist for selecting and passing one of the tapped voltages, namely tree decoding and binary decoding.
FIG. 2 is a schematic diagram of a conventional 3-bit tree decoding VDAC 20 adapted to include, in part, a total of (23+1−2=14) CMOS transistor switches 41–48, 61–64, 81–82, as well as half as many CMOS inverters 51–54, 71–72 and 81. Resistor 22 is divided into 8 equal resistive segments 22a, 22b, . . . 22h. Three decoding stages 40, 60 and 80 are used. Stage 40 receives the eight tapped voltages present on nodes a, b, c, d, . . . , h and delivers four of these voltage to the four shown nodes i, j, k, l, in response to bit b0 of the three-bit word b2b1b0. Stage 60 receives the voltages present on nodes i, j, k, l, and delivers two of these voltages to nodes m, n in response to bit b1 of the three-bit word b2b1b0. Stage 80 receives the two voltages present on nodes m, n, and delivers one of these voltages as the output voltage to output terminal Vout in response to bit b2 of the three-bit word b2b1b0. Therefore, depending on the value of the three bits of word b2b1b0, one of the tapped voltages present on nodes a, b, c . . . , h is passed to output terminal Vout.
One disadvantage of tree decoding VDACs, such as VDAC 20, is that the signal path from any one of the tapped voltages to the output terminal includes the junction capacitance and the series on-resistance of the closed transistor switches disposed along the path, as well as the junction capacitance of some of the open transistor switches coupled to that path. For example, the path from tapped node a to terminal Vout includes the junction capacitance and on-resistance of transistor switches 41, 61, 81, as well as junction capacitance of 42 and 62. Accordingly, tree decoding VDACs are typically used in applications where speed of operation is not relatively critical.
FIG. 3 is a schematic diagram of a conventional 3-bit binary decoding VDAC 100 adapted to include, in part, a total of (23=8) CMOS transistor switches 91–98. VDAC 100 includes one decoding stage 90 in which 8 switches are disposed. A decoder (not shown) receives the three-bit word b2b1b0 and generates 8 signals z0, z1, . . . z8 that are respectively applied to switches 91–98. Depending on the three bits of word b2b1b0, one of the eight shown signals z0–z8 is asserted, in order to pass one of the tapped voltages present on nodes a, b, c . . . , h to output terminal Vout. Because in such VDACs, one switch is used per tapped node, the signal path from each tapped node to the output terminal sees relatively less resistance. However, such a VDAC requires a relatively large amount of decoding, particularly as the number of bits in word b2b1b0 increases. Furthermore, neither VDAC 20 nor VDAC 100 is adapted to perform differential digital-to-analog voltage conversion.